The present invention relates to a semiconductor memory device, and, more particularly, to a semiconductor memory device with a redundancy circuit.
Demands for miniaturization, larger capacity and lower power consumption of semiconductor memory devices make it hard to fabricate semiconductor memory devices having defectless memories. To prevent the yield from dropping, a semiconductor memory device has a redundancy circuit.
FIGS. 1 and 2 are exemplary diagrams of a semiconductor memory device 1 such as Synchronous Dynamic Random Access Memory (SDRAM) having a conventional shift redundant type redundancy circuit. The semiconductor memory device 1 has 16 data bus lines DB0 to DB15 and a single redundancy data bus line DBs. First to sixteenth shift switches SW0 to SW15 are respectively located between the associated data bus lines DB0-DB15 and associated first to sixteenth input/output data lines DQ0 to DQ15. Each of the first to sixteenth shift switches SW0-SW15 is switched between an original position at which it connects the associated one of the first to sixteenth input/output data lines DQ0-DQ15 to the associated one of the first to sixteenth data bus lines DB0-DB15 and a shift position at which it connects the associated one of the first to sixteenth input/output data lines DQ0-DQ15 to the associated one of the second to sixteenth data bus lines DB1-DB15, higher by one bit than the associated input/output data line, and the redundancy data bus line DBs. For example, the sixteenth shift switch SW15 connects the sixteenth input/output data line DQ15 to the sixteenth data bus line DB15 or the redundancy data bus line DBs.
The switching actions of the first to sixteenth shift switches SW0-SW15 are controlled by a column redundancy address decoder 11 and a shift-switch changeover signal generator 12 both shown in FIG. 2. The redundancy address decoder 11 decodes a redundancy address signal and supplies the signal generator 12 with a changeover control signal which has bits corresponding in number to the first to sixteenth shift switches SW0-SW15.
The signal generator 12 has first to sixteenth transfer gates TG0-TG15 and a redundancy transfer gate TGs connected in series between a high-potential power supply VDD and a low-potential power supply VSS. Changeover signals which control the switching of the first to sixteenth shift switches SW0-SW15 are output from the individual nodes between the transfer gates TG0-TG15 and TGs. Each of the first to sixteenth shift switches SW0-SW15 is set to the original position in response to an H-level changeover signal and is set to the shift position in response to an L-level changeover signal.
When there is a defective memory cell connected to the fourteenth data bus line DB13, for example, the redundancy address signal that indicates the defective memory cell is supplied to the redundancy address decoder 11. The redundancy address decoder 11 supplies the signal generator 12 with the changeover signal which turns the transfer gate TG13 off and turns the redundancy transfer gate TGs on. This switching control sets the fourteenth to sixteenth shift switches SW13-SW15 to the shift positions (shift redundant operation). As a result, the fourteenth input/output data line DQ13 is connected to the fifteenth data bus line DB14, the fifteenth input/output data line DQ14 is connected to the sixteenth data bus line DB15, and the sixteenth input/output data line DQl5 is connected to the redundancy data bus line DBs.
In other words, the defective data bus line DB13 is switched to the normal upper-bit data bus line and the redundancy data bus line in the shift redundant system.
To meet the demands for a larger capacity and higher data transfer rate, the semiconductor memory device 1 is provided with a greater number of data bus lines. The increased number of data bus lines makes the time needed for the switching of the shift switches longer. Specifically, an RC delay occurs due to the ON resistances of the individual transfer gates TG0-TG15 and TGs, the capacitances of the lines that connect the individual shift switches SW0-SW15 and the junction capacitances of the transfer gates TG0-TG15 and TGs.
According to a column redundant method including row address information or so-called row flexible redundant method, particularly, a row address is determined first, then a column address is determined after which a shift redundant operation starts. Data reading or writing is initiated after switching of the shift switches is completed. Therefore, a delay in the switching of the shift switches makes the time needed for data reading or writing longer, thus delaying the operation of the semiconductor memory device 1.
Accordingly, it is an object of the present invention to provide a semiconductor memory device with a shift redundancy circuit which has a shortened redundancy operation.
The first aspect of the present invention provides a semiconductor memory device including a plurality of input/output data lines, a plurality of data bus lines, at least one redundancy data bus line, a plurality of shift switches, and a changeover signal generating circuit connected to the plurality of shift switches. The shift switches switch connections of the plurality of input/output data lines and a first group of the plurality of data bus lines to connections of the plurality of input/output data lines and a second group of the data bus lines, which exclude at least one defective data bus line, and the at least one redundancy data bus line in response to a plurality of changeover signals. The changeover signal generating circuit generates the plurality of changeover signals including a first group of changeover signals and a second group of changeover signals in response to a redundancy address signal. The changeover signal generating circuit has a plurality of signal generating blocks including a first signal generating block for generating the first group of changeover signals and a second signal generating block for generating the second group of changeover signals.
The second aspect of the present invention provides a semiconductor memory device including a plurality of input/output data lines, a plurality of data bus lines, at least one redundancy data bus line, a plurality of shift switches, a decoder circuit for decoding a redundancy address signal and generating a decoded redundancy address signal, and a changeover signal generating circuit connected to the decoder circuit and the plurality of shift switches. The shift switches switch connections of the plurality of input/output data lines and a first group of the plurality of data bus lines to connections of the plurality of input/output data lines and a second group of the data bus lines, which exclude at least one defective data bus line and the at least one redundancy data bus line in response to a plurality of changeover signals. The changeover signal generating circuit generates the plurality of changeover signals including a first group of changeover signals and a second group of changeover signals in response to the decoded redundancy address signal. The changeover signal generating circuit has a plurality of signal generating blocks including a first signal generating block for generating the first group of changeover signals and a second signal generating block for generating the second group of changeover signals. Each signal generating block includes a plurality of switches which are connected in series between a high-potential power supply and a low-potential power supply and are turned on or off in response to the decoded redundancy address signal.
This invention further provides a method of performing a redundancy process for compensating a semiconductor memory device for a defective memory cell. The method of the present invention entails the following steps: decoding a redundancy address signal and generating a decoded redundancy address signal; generating a plurality of changeover signals including a first group of changeover signals and a second group of changeover signals by operating a plurality of signal generating blocks in response to the decoded redundancy address signal; and switching connections of a plurality of input/output data lines and a first group of a plurality of data bus lines to connections of the plurality of input/output data lines and a second group of the data bus lines, which exclude at least one defective data bus line, and at least one redundancy data bus line by operating a plurality of shift switches in response to the plurality of changeover signals.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.